VLSI Titles

IEEE 2017-2018 ECE project titles download

Code Titles IEEE/Year Abstract
REVLSI-1 AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC 2017 Download
REVLSI-2 AGING-AWARE RELIABLE MULTIPLIER DESIGN WITH ADAPTIVE HOLD LOGIC 2017 Download
REVLSI-3 Design of Optimized High Speed FIR Filter 2017 Download
REVLSI-4 A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications 2017 Download
REVLSI-5 Area Efficient Parallel Fir Digital Filter Structures For Symmetric Convolutions Based On Fast Fir Algorithm 2017 Download
REVLSI-6 Low Adaptation Delay in Fixed Point LMS Adaptive Filter for DSP Applications 2017 Download
REVLSI-7 Delay Analysis for Current Mode Threshold Logic Gate Designs 2017 Download
REVLSI-8 Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops 2017 Download
REVLSI-9 Register-Less NULL Convention Logic 2017 Download
REVLSI-10 Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders 2017 Download
REVLSI-11 Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique 2017 Download
REVLSI-12 Dual-Quality 4: 2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers 2017 Download
REVLSI-13 Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields 2017 Download
REVLSI-14 Area-Efficient Architecture for Dual-Mode Double Precision Floating Point Division 2017 Download
REVLSI-15 Reconfigurable Constant Multiplication for FPGAs 2017 Download
REVLSI-16 On the VLSI Energy Complexity of LDPC Decoder Circuit 2017 Download
REVLSI-17 On the VLSI Energy Complexity of LDPC Decoder Circuit 2017 Download
REVLSI-18 Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication 2017 Download
REVLSI-19 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 2017 Download
REVLSI-20 A General Digit-Serial Architecture for Montgomery Modular Multiplication 2017 Download
REVLSI-21 Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems 2017 Download
REVLSI-22 Design of Power and Area Efficient Approximate Multipliers 2017 Download
REVLSI-23 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder 2017 Download
REVLSI-24 Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication 2017 Download
REVLSI-25 Probability-Driven Multibit Flip-Flop Integration With Clock Gating 2017 Download
REVLSI-26 A Bit-Plane Decomposition Matrix-Based VLSI Integer Transform Architecture for HEVC 2017 Download
REVLSI-27 Resource-Efficient SRAM-based Ternary Content Addressable Memory 2017 Download
REVLSI-28 High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder 2017 Download
REVLSI-29 Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST 2017 Download
REVLSI-30 MAC Unit for Reconfigurable Systems Using Multi-Operand Adders with Double Carry-Save Encoding 2017 Download